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Ordering number : EN5625A
Monolithic Digital IC
LB1872
Polygon Mirror Scanner Driver IC
Overview
The LB1872 is a 3-phase brushless motor driver IC developed for driving the polygon mirror motor used in laser printers and similar products.
braking (free running when stopped) * Built-in FG and error amplifiers * Full complement of protection circuits, including thermal protection, low voltage protection, and current limiter circuits, provided on chip.
Functions and Features
* Integrates the circuits (speed control and driver circuits) required for laser printer polygon mirror motor drive in a single chip. * Uses a current linear drive technique for minimal motor noise. Only a small capacitors are required for output oscillation prevention. * PLL speed control adopted for high-precision rotation with excellent jitter characteristics. * Phase lock detection output with a chattering prevention function * Four rotation rates can be set up using a single crystal oscillator to support 240, 300, 400, and 600 dpi operation. * Arbitrary rotation rates can be acquired when an external clock is used. * Deceleration function implemented by short-circuit
Package Dimensions
unit: mm 3147B-DIP28H
[LB1872]
SANYO: DIP28H
Allowable power dissipation, Pd max - W
With an arbitrarily large heat sink
Independent IC
Ambient temperature, Ta - C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN
13098HA(OT) No. 5625-1/11
LB1872
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Maximum output current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg t 0.5s Independent IC Arbitrarily large heat sink Conditions Ratings 30 2.0 3 20 -20 to +80 -55 to +150 Unit V A W W C C
Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage 5.0-V fixed-voltage output current LD pin voltage FGS pin voltage LD pin output current FGS pin output current Symbol VCC IREG VLD VFGS ILD IFGS Conditions Ratings 10 to 28 0 to -15 0 to 28 0 to 28 0 to 10 0 to 5 Unit V mA V V mA mA
Electrical Characteristics at Ta = 25C, VCC = 24 V
Parameter Current drain [Output Saturation Voltage] VAGC = 2 V Source V(sat)1-1 IO = 0.7 A, RF = 0 V(sat)1-2 IO = 1.5 A, RF = 0 V(sat)2-1 IO = 0.7 A, RF = 0 V(sat)2-2 IO = 1.5 A, RF = 0 IO (leak) VREG VREG1 VREG2 VREG3 IB(HA) VHIN VICM VIOH VSD VSD TSD TSD VIO(FG) IB(FG) VB(FG) VOH(FG) VOL(FG) VSHL VSLH VFGL VFGSIL 100 400 IOH = -500 A IOL = 500 A Design target value (junction temperature) Design target value (junction temperature) VCC = 10 to 28 V IO = 0 to 10 mA Design target value VCC = 28 V 4.65 5.0 40 20 0 1.5 1.8 0.3 0.7 1.9 2.2 0.5 1.0 100 V V V V A Symbol ICC In stop mode Conditions Ratings min typ 20 max 27 Unit mA
Sink Output leakage current [5-V Fixed-Voltage Output] Output voltage Voltage regulation Load regulation Temperature coefficient [Hall Input Block] Input bias current Differential-mode input range Common-mode input range Input offset voltage [Low Voltage Protection Circuit] Operating voltage Hysteresis [Thermal Protection Circuit] Shutdown temperature Hysteresis [FG Amplifier] Input offset voltage Input bias current DC bias level Output high-level voltage Output low-level voltage [FG Schmitt Input Block] Input hysteresis (high to low) Input hysteresis (low to high) Hysteresis Input operating level
5.35 100 100
V mV mV mV/C
VAGC = 3 V With a sine wave input Differential input: 50 mV p-p Design target value 50 3.5 -20
2
10 350 VCC - 3.5 +20
A mV V mV
8.4 0.2
8.8 0.4
9.2 0.6
V V
150
180 40
C C
Design target value
-10 -1 -5% 1/2VREG 0.8
+10 +1 +5%
mV A V V
VREG - 1.2 VREG - 0.8 1.2
V
0 150 150 200
mV mV mV mV
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No. 5625-2/11
LB1872
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Parameter Output saturation voltage Output leakage current [Error Amplifier] Input offset voltage Input bias current DC bias level Output high-level voltage Output low-level voltage [Phase Comparator Output] Output high-level voltage Output low-level voltage Output source current Output sink current [Lock Detection Output] Output saturation voltage Output leakage current [Drive Block] Output idling voltage Forward gain Current limiter Brake command voltage [Reference Signal Block] Crystal oscillator frequency Low-level pin voltage High-level pin voltage [N1 Pin] External input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current [N2 Pin] High-level input voltage Middle-level input voltage Low-level input voltage Input open voltage High-level input current Low-level input current [S/S Pin] High-level input voltage Low-level input voltage Input open voltage Hysteresis High-level input current Low-level input current [CLD Pin] Charge current Discharge current ICLD1 ICLD2 VCLD = 0 V (Phase locked) VCL = VREG/2 (Phase unlocked) -9 1 -7 -5 A mA VIH(SS) VIL(SS) VIO(SS) VIS(SS) IIH(SS) IIL(SS) VS/S = VREG VS/S = 0 V 3.5 0 VREG - 0.5 0.3 -10 -350 0.4 0 -275 VREG 1.5 VREG 0.5 +10 V V V V A A VIH(N2) VIM(N2) VIL(N2) VIO(N2) IIH(N2) IIL(N2) VN2 = VREG VN2 = 0 V -270 4.0 2.0 0 2.2 2.5 200 -200 VREG 3.0 1.0 2.8 270 V V V V A A fI(N1) VIH(N1) VIL(N1) VIO(NI) VIS(N1) IIH(N1) IIL(N1) VN1 = VREG VN1 = 0 V In external clock mode 100 3.5 0 VREG - 0.5 0.3 -10 -350 0.4 0 -275 10000 VREG 1.5 VREG 0.5 +10 Hz V V V V A A fOSC VOSCL IOSCH In crystal oscillator mode IOSC = -0.5 mA VOSC = VOSCL + 0.3 V 1 1.7 0.5 10 MHz V mA VID GDF1 GDF2 VL VBRK When the phase is locked When unlocked Rf = 2 0.4 2.4 0.45 0.5 3.0 0.5 2.3 6 0.6 3.6 0.55 V V mV VLD(sat) ILDLEAK ILD = 5 mA VCC = 28 V 0.1 0.4 10 V A VPDH VPDL IPD+ IPD- IOH = -100 A IOL = 100 A VPD = VREG/2 VPD = VREG/2 1.5 VREG - 0.2 VREG - 0.1 0.1 0.2 -0.6 V V mA mA VIO(ER) IB(ER) VB(ER) VOH(ER) VOL(ER) IOH = -500 A IERI = 100 A, IOL = 500 A Design target value -10 -1 -5% 1/2VREG 1.0 +10 +1 +5% mV A V V 1.3 V Symbol VFGS(sat) IL(FGS) IFGS = 3 mA VCC = 28 V Conditions Ratings min typ 0.2 max 0.4 10 Unit V A
VREG - 1.2 VREG - 0.8 0.7
No. 5625-3/11
LB1872 Pin Assignment Clock Divisor Switching
N1 H H L L CLK IN N2 H L H L M or open Divisor 2048 (4 x 1 x 512) 4096 (4 x 2 x 512) 5120 (5 x 2 x 512) 3072 (3 x 2 x 512) EXT. CLK
Three-Phase Logic Truth Table
H1 H H H L L L H2 L L H H H L H3 H L L L H H OUT1 L L M H H M OUT2 H M L L M H OUT3 M H H M L L
No. 5625-4/11
LB1872 Equivalent Circuit Block Diagram
No. 5625-5/11
LB1872 Pin Functions
Pin No. Symbol Pin function Equivalent circuit
1 2 3 4 5 6
IN3- IN3
+
Hall amplifier inputs IN+ > IN- is the input high state, and the reverse is the input low state. Connect a capacitor between the IN+ and IN- inputs if there is noise in the Hall sensor signals. An amplitude of over 50 mV p-p and under 350 mV p-p is desirable in the Hall sensor signals. Kickback may occur in the output if the input signal has an amplitude greater than 350 mV p-p.
IN1- IN1+ IN2- IN2
+
7 8 9
OUT3 OUT2 OUT1
Motor drive outputs Connect capacitors between the motor outputs (or between the motor outputs and ground) if oscillation occurs in the outputs. (Use capacitors in the range 0.1 F to 0.47 F.)
Output current detection 10 RF Connect a resistor (Rf) between this pin and ground. The output current is limited to be up to IOUT = VREG/Rf.
11
VCC
Power supply
Stabilized power supply output (5-V output) 12 VREG Connect a capacitor (about 0.1 F) between this pin and ground for stabilization.
Crystal oscillator connections 13 14 XO XI These pins are used to drive the reference clock oscillator element. If an external clock (with a frequency of a few MHz) is used, connect a resistor (about 13 k) to the XI pin in series and input the clock signal through that resistor. Leave the XO pin open in this case.
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No. 5625-6/11
LB1872
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Pin No. Symbol Pin function Equivalent circuit
Control amplifier frequency correction 15 FC Current limiter system closed loop oscillation can be prevented by inserting a capacitor (about 0.022 to 0.47 F) between this pin and ground. If the capacitance of this capacitor is too large, the output current response characteristics may be degraded.
16
EO
Error amplifier output When high, the output current is increased. Control amplifier
17
EI
Error amplifier input
Phase comparator output (PLL output) 18 PD The phase error is output as changes in the duty of a pulse waveform. The output current is increased as the duty becomes smaller.
LD output mask time setting 19 CLD Chattering can be masked by inserting a capacitor (about 0.1 to 0.47 F) between this pin and ground. The startup time may be increased if only masking is used and the servo constants are not re-optimized.
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No. 5625-7/11
LB1872
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Pin No. Symbol Pin function Equivalent circuit
Phase lock detector output 20 LD This pin goes to the on state when the PLL phase is locked. This is an open collector output.
Divisor switch Low: 0 to 1.0 V 21 N2 Middle: 2.0 to 3.0 V High: 4.0 V to VREG This pin goes to the middle level when open.
Divisor switch and external clock input Low: 0 to 1.5 V 22 N1 High: 3.5 V to VREG This pin functions as the external clock input pin when N2 is at the middle level. This pin goes to the high level when open.
Start/stop control 23 S/S Low: Start High: Stop This pin goes to the high level when open.
FG pulse-converted output 24 FGS This pin outputs the post-hysteresis comparator FG signal. This is an open collector output.
FG amplifier output 25 FGOUT If noise in the FG signal is a problem, e.g. if discharge noise is detected, insert a capacitor (about 0.01 to 0.1 F) between this pin and ground.
FG schmitt comparator
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No. 5625-8/11
LB1872
Continued from preceding page.
Pin No. Symbol Pin function Equivalent circuit
26
FGIN-
FG amplifier input
27
AGC
AGC amplifier frequency characteristics correction Insert a capacitor (about 0.1 F) between this pin and ground.
28
GND
Ground
LB1872 Functional Description 1. Speed control circuit Since this IC adopts a PLL speed control circuit, it can provide high-precision, jitter-free, and stable motor operation. This PLL circuit compares the phases of the CLK (external clock) rising edge and the FG Schmitt output rising edge and uses the error output from that comparison for control. If an internal clock system is used, the FG servo frequency is determined by the following formula. Therefore, the motor speed can be set by setting the number of FG pulses and the crystal oscillator frequency. fFG(servo) = fOSC/N fOSC: Crystal oscillator frequency N: Clock divisor (See the separately provided table.) If an external clock (input to the N1 pin) is used, the IC controls the motor speed by holding the FG servo frequency identical to the external clock frequency. 2. Output drive circuit To suppress motor noise as much as possible, this IC adopts a three-phase full wave current linear drive technique. Also, it adopts a midpoint control technique to prevent ASO destruction of the output transistors. This IC uses short-circuit braking (lower side output) for motor deceleration during speed switching and lock pull in. In stop mode, the output is turned off. If a motor with a coil resistance (interphase) of 10 or lower is used, diodes (rectifying) may be inserted between the outputs and ground (for all outputs) and current limitation may also be applied during braking to prevent excessive braking currents. Although this is disadvantageous from an ASO standpoint, since states with a large back EMF are states with a high switching frequency and the amount of time during which loads are applied to the transistors will be shorter, ASO problems will not be particular severe. 3. Current limiter circuit The current limiter circuit is a peak current limiter whose limit current is determined by I = VRF/Rf (where VRF = 0.5 V (typical) and Rf is the current detection resistor).
No. 5625-9/11
LB1872 4. Reference clock Any one of the following three techniques can be used to input the reference clock used for speed control. * Crystal oscillator generated clock Use the following circuit, consisting of a crystal element, capacitors, and resistors, as a crystal oscillator circuit. C1 and R1: Used for oscillator stabilization. C3: Used for oscillator element coupling. C2: Used for overtone prevention. R2: Improves the oscillator margin.
Sample External Component Values
Oscillator frequency (MHz) 1 to 3 3 to 5 5 to 7 7 to 10 C1 (F) 0.1 0.1 0.1 0.1 C2 (pF) 47 18 -- -- C3 (pF) 220 100 47 33 R1 () 220 k 100 k 47 k 10 k R2 () -- -- -- 4.7 k
This circuit and these component values are only provided for reference purposes. Consult with the manufacturer of the crystal element concerning the influence of such factors as the characteristics of the crystal element itself and the stray capacitances due to the printed circuit board wiring pattern to assure that problems do not occur. (Notes on printed circuit board wiring) Since crystal oscillator circuits are high-frequency circuits, they are easily influenced by stray capacitances due to the printed circuit board wiring. Therefore, lines for external components must be kept as short as possible and lines must be made as narrow as possible. In this external circuit, the connection between the oscillator element and C3 (and C2) is particularly subject to influence by stray capacitance, and requires special care. * External clock (crystal oscillator equivalent: a few MHz) If a signal equivalent to a crystal oscillator signal is input from an external signal generator, input that signal through a series resistor of about 13 k to the XI pin. Leave the XO pin open. * External clock (FG frequency equivalent: a few kHz) If a signal equivalent to the FG frequency is input from an external signal generator, set the N2 pin to the middle level (or open) and input that signal to the N1 pin. In this case, the motor will remain in the stopped state (shortcircuit braking operation) even if a start input is applied when no clock is input. However, since IC heating due to the large output drive currents that flow in the short braking state (since the lower side transistors in all phases are driven) care is required if the braking state must be held for extended periods. 5. Hall input signals Even if the amplitude of the Hall sensor input signals is changed by the motor, the influence on the output will be suppressed by the AGC circuit. However, if there are discrepancies between the amplitudes of the three phases, the output phase switching timing may be shifted. The output current will be cut off by a protection circuit if a start signal is input when there are no signals applied to the Hall inputs. The maximum operating frequency of the Hall inputs is affected by the saturation state of the outputs. While there are no problems for frequencies of under 1 kHz (the frequency in a single Hall phase), if a higher operating frequency is required, it can be advantageous if the outputs remain unsaturated. If the outputs remain in the unsaturated state, this IC can be used up to frequencies of about 2 kHz. Since motors with higher speeds have higher operating frequencies, we recommend using motors with four motor magnet poles. 6. LD output The LD output goes on when the phase is locked. Phase lock is determined not by the speed error but by the phase error only. Therefore, the speed error when the LD output is on, during, for example, lock pull-in, will change with the acceleration of the FD signal. (The speed error will be smaller for lower accelerations.) If it is necessary to
No. 5625-10/11
LB1872 stipulate the speed error when the LD output is on, this must be determined based on the result of a speed measurement for the motor state. This IC includes a built-in circuit that masks LD output chattering (rapid switching between on and off) during phase lock pull-in. The mask time is determined as shown below by the capacitance of the capacitor inserted between the CLD pin and ground. t = 0.35 x C t: Mask time (s) C: External capacitance (F) If LD chattering is masked, the LD output is delayed by the mask time. Therefore care is required, since the speed error when LD is on is changed by the mask time. Leave the CLD pin open if there is no need for masking. 7. Power supply stabilization Since this IC provides large output currents, it can easily cause fluctuations in the power supply line voltage. Therefore, capacitors with adequate capacitances for stabilization must be inserted between the VDD and ground pins. If diodes are inserted in the power supply lines to prevent device destruction by reverse power supply connection, the power supply line voltage becomes especially liable to fluctuations. In this case, even larger capacitors are required. 8. External protection circuits If an application will include external motor constraint protection and other external protection circuits, use an open collector transistor output to set the FC pin low to shut off the IC drive current.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1998. Specifications and information herein are subject to change without notice. PS No. 5625-11/11

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